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PSoC(R) Mixed-Signal Array
Automotive: CY8C29466 and CY8C29666
Final Data Sheet
Features
Powerful Harvard Architecture Processor M8C Processor Speeds to 12 MHz Two 8x8 Multiply, 32-Bit Accumulate Low Power at High Speed 4.75V to 5.25V Operating Voltage Automotive Temp. Range: -40C to +125C Advanced Peripherals (PSoC Blocks) 12 Rail-to-Rail Analog PSoC Blocks Provide: - Up to 14-Bit ADCs - Up to 9-Bit DACs - Programmable Gain Amplifiers - Programmable Filters and Comparators 16 Digital PSoC Blocks Provide: - 8- to 32-Bit Timers, Counters, and PWMs - CRC and PRS Modules - Up to 4 Full-Duplex UARTs - Multiple SPITM Masters or Slaves - Connectable to all GPIO Pins Complex Peripherals by Combining Blocks Precision, Programmable Clocking Internal 4% 24 MHz Oscillator 24 MHz with Optional 32.768 kHz Crystal Optional External Oscillator, up to 24 MHz Internal Oscillator for Watchdog and Sleep Flexible On-Chip Memory 32K Bytes Flash Program Storage 100 Erase/Write Cycles 2K Bytes SRAM Data Storage In-System Serial Programming (ISSP) Partial Flash Updates Flexible Protection Modes Programmable Pin Configurations 25 mA Sink on All GPIO Pull Up, Pull Down, High Z, Strong, or Open Drain Drive Modes on all GPIO Up to 12 Analog Inputs on GPIO Four 30 mA Analog Outputs on GPIO Configurable Interrupt on All GPIO Additional System Resources I2CTM Slave, Master, and Multi-Master to 400 kHz Watchdog and Sleep Timers User-Configurable Low Voltage Detection Integrated Supervisory Circuit On-Chip Precision Voltage Reference Complete Development Tools Free Development Software (PSoCTM Designer) Full-Featured, In-Circuit Emulator and Programmer Full Speed Emulation Complex Breakpoint Structure 128K Bytes Trace Memory Complex Events C Compilers, Assembler, and Linker
PSoC CORE
Port 5 Port 4 Port 3 Port 2 Port 1 Port 0
Analog Drivers
PSoC(R) Functional Overview
The PSoC(R) family consists of many Mixed-Signal Array with On-Chip Controller devices. These devices are designed to replace multiple traditional MCU-based system components with one, low cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic, as well as programmable interconnects. This architecture allows the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pinouts and packages. The PSoC architecture, as illustrated on the left, is comprised of four main areas: PSoC Core, Digital System, Analog System, and System Resources. Configurable global busing allows all the device resources to be combined into a complete custom system. The PSoC CY8C29x66 automotive family can have up to six IO ports that connect to the global digital and analog interconnects, providing access to 16 digital blocks and 12 analog blocks.
SYSTEM BUS
Global Digital Interconnect SRAM 2K Interrupt Controller SROM
Global Analog Interconnect Flash 32K Sleep and Watchdog
CPU Core (M8C)
Multiple Clock Sources (Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
ANALOG SYSTEM
Analog Ref.
Digital Block Array
Analog Block Array
Analog Input Muxing
The PSoC Core
Digital Clocks Two Multiply Accums. POR and LVD Decimator I2C System Resets Internal Voltage Ref.
The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO (General Purpose IO). The M8C CPU core is a powerful processor with speeds up to 12 MHz, providing a two MIPS 8-bit Harvard architecture micro-
SYSTEM RESOURCES
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CY8C29x66 Automotive Data Sheet processor. The CPU utilizes an interrupt controller with 25 vectors, to simplify programming of real time embedded events. Program execution is timed and protected using the included Sleep and Watch Dog Timers (WDT). Memory includes 32K of Flash for program storage and 2K of SRAM for data storage. Program Flash utilizes four protection levels on blocks of 64 bytes, allowing customized software IP protection. The PSoC device incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate to 4% over temperature and voltage. A low power 32 kHz ILO (internal low speed oscillator) is provided for the Sleep timer and WDT. If crystal accuracy is desired, the ECO (32.768 kHz external crystal oscillator) is available for use as a Real Time Clock (RTC) and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. The clocks, together with programmable clock dividers (as a System Resource), provide the flexibility to integrate almost any timing requirement into the PSoC device. PSoC GPIOs provide connection to the CPU, digital and analog resources of the device. Each pin's drive mode may be selected from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read.
PSoC(R) Overview
Port 5 Port 4
Port 3 Port 2
Port 1 Port 0
Digital Clocks From Core
To System Bus
To Analog System
DIGITAL SYSTEM
Digital PSoC Block Array
Row Input Configuration
Row 0
DBB00 DBB01 DCB02
4 DCB03 4
Row Output Configuration
8 8 Row Input Configuration
8
Row 1
DBB10 DBB11 DCB12
4 DCB13 4
8 Row Output Configuration
Row Input Configuration
Row 2
DBB20 DBB21 DCB22
4 DCB23 4
Row Output Configuration
Row Input Configuration
Row 3
DBB30 DBB31 DCB32
4 DCB33 4
Row Output Configuration
The Digital System
The Digital System is composed of 16 digital PSoC blocks. Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. Digital peripheral configurations include those listed below.

GIE[7:0] GIO[7:0]
Global Digital Interconnect
GOE[7:0] GOO[7:0]
PWMs (8 to 32 bit) PWMs with Dead Band (8 to 32 bit) Counters (8 to 32 bit) Timers (8 to 32 bit) UART 8 bit with selectable parity (up to 4) SPI Master and Slave (up to 4 each) I2C Slave and Multi-Master (1 available as a System Resource) Cyclical Redundancy Checker/Generator (8 to 32 bit) IrDA (up to 4) Pseudo Random Sequence Generators (8 to 32 bit)
Digital System Block Diagram
The Analog System
The Analog System is composed of 12 configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the more common PSoC analog functions (most available as user modules) are listed below.

Analog-to-digital converters (up to 4, with 6- to 14-bit resolution, selectable as Incremental, Delta Sigma, and SAR) Filters (2, 4, 6, or 8 pole band-pass, low-pass, and notch) Amplifiers (up to 4, with selectable gain to 48x) Instrumentation amplifiers (up to 2, with selectable gain to 93x) Comparators (up to 4, with 16 selectable thresholds) DACs (up to 4, with 6- to 9-bit resolution) Multiplying DACs (up to 4, with 6- to 9-bit resolution) High current output drivers (four with 40 mA drive as a PSoC Core resource) 1.3V reference (as a System Resource) DTMF Dialer 2

The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This allows you the optimum choice of system resources for your application. Family resources are shown in the table titled "PSoC Device Characteristics" on page 3.

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CY8C29x66 Automotive Data Sheet Modulators Correlators Peak Detectors Many other topologies possible
PSoC(R) Overview

Additional System Resources
System Resources, some of which have been previously listed, provide additional capability useful to complete systems. Additional resources include a multiplier, decimator, switch mode pump, low voltage detection, and power on reset. Brief statements describing the merits of each system resource are presented below.
Analog blocks are provided in columns of three, which includes one CT (Continuous Time) and two SC (Switched Capacitor) blocks, as shown in the figure below.
P0[7] P0[5] P0[3] P0[1] AGNDIn RefIn P0[6] P0[4] P0[2] P0[0] P2[6]
Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers. Two multiply accumulates (MACs) provide fast 8-bit multiplier with 32-bit accumulate to assist in both general math as well as digital filters. The decimator provides a custom hardware filter for digital signal, processing applications including the creation of Delta Sigma ADCs. The I2C module provides 100 and 400 kHz communication over two wires. Slave, master, and multi-master modes are all supported. Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. An internal 1.3 voltage reference provides an absolute reference for the analog system, including ADCs and DACs.
P2[3]
P2[4] P2[2] P2[0]
P2[1]
Array Input Configuration
PSoC Device Characteristics
ACI0[1:0] ACI1[1:0] ACI2[1:0] ACI3[1:0]
Block Array
ACB00 ASC10 ASD20 ACB01 ASD11 ASC21 ACB02 ASC12 ASD22 ACB03 ASD13 ASC23
Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4 analog blocks. The following table lists the resources available for specific PSoC device groups. The PSoC device covered by this data sheet is highlighted below. PSoC Device Characteristics
Analog Columns Analog Outputs Analog Inputs Analog Blocks Digital Blocks Digital IO Digital Rows SRAM Size
PSoC Part Number CY8C29x66 CY8C27x43
AGNDIn RefIn Bandgap
Analog Reference
Interface to Digital System RefHi RefLo AGND Reference Generators
up to 64 up to 44 56 up to 24 up to 28 16 up to 28
4 2 1 1 1 1 0
16 8 4 4 4 4 0
12 12 48 12 28 8 28
4 4 2 2 0 0 0
4 4 2 2 2 2 0
12 12 6 6 4a 4a 3b
2K 256 Bytes 1K 256 Bytes 512 Bytes 256 Bytes 512 Bytes
CY8C24x94 CY8C24x23A
M8C Interface (Address Bus, Data Bus, Etc.)
CY8C21x34 CY8C21x23 CY8C20x34
Analog System Block Diagram
a. Limited analog functionality. b. Two analog blocks and one CapSense.
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Flash Size
32K 16K 16K 4K 8K 4K 8K
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CY8C29x66 Automotive Data Sheet
PSoC(R) Overview
Getting Started
The quickest path to understanding the PSoC silicon is by reading this data sheet and using the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in-depth information, along with detailed programming information, reference the PSoC Mixed-Signal Array Technical Reference Manual. For up-to-date Ordering, Packaging, and Electrical Specification information, reference the latest PSoC device data sheets on the web at http://www.cypress.com/psoc.
Development Tools
PSoC Designer is a Microsoft(R) Windows-based, integrated development environment for the Programmable System-onChip (PSoC) devices. The PSoC Designer IDE and application runs on Windows NT 4.0, Windows 2000, Windows Millennium (Me), or Windows XP. (Reference the PSoC Designer Functional Flow diagram below.) PSoC Designer helps the customer to select an operating configuration for the PSoC, write application code that uses the PSoC, and debug the application. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and the CYASM macro assembler for the CPUs. PSoC Designer also supports a high-level C language compiler developed specifically for the devices in the family.
Development Kits
Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store contains development kits, C compilers, and all accessories for PSoC development. Go to the Cypress Online Store web site at http://www.cypress.com, click the Online Store shopping cart icon at the bottom of the web page, and click PSoC (Programmable System-on-Chip) to view a current list of available items.
PSoC Designer
Graphical Designer Interface
Context Sensitive Help
Technical Training Modules
Free PSoC technical training modules are available for users new to PSoC. Training modules cover designing, debugging, advanced analog and CapSense. Go to http:// www.cypress.com/techtrain.
Commands
Results
Importable Design Database Device Database Application Database Project Database User Modules Library PSoC Configuration Sheet
Consultants
Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to http://www.cypress.com, click on Design Support located on the left side of the web page, and select CYPros Consultants.
PSoC Designer Core Engine
Manufacturing Information File
Technical Support
PSoC application engineers take pride in fast and accurate response. They can be reached with a 4-hour guaranteed response at http://www.cypress.com/support/login.cfm.
Application Notes
A long list of application notes will assist you in every aspect of your design effort. To view the PSoC application notes, go to the http://www.cypress.com web site and select Application Notes under the Design Resources list located in the center of the web page. Application notes are listed by date by default.
Emulation Pod In-Circuit Emulator Device Programmer
PSoC Designer Subsystems
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CY8C29x66 Automotive Data Sheet
PSoC(R) Overview
PSoC Designer Software Subsystems
Device Editor
The Device Editor subsystem allows the user to select different onboard analog and digital components called user modules using the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time. PSoC Designer sets up power-on initialization tables for selected PSoC block configurations and creates source code for an application framework. The framework contains software to operate the selected components and, if the project uses more than one operating configuration, contains routines to switch between different sets of PSoC block configurations at run time. PSoC Designer can print out a configuration sheet for a given project configuration for use during application programming in conjunction with the Device Data Sheet. Once the framework is generated, the user can add application-specific code to flesh out the framework. It's also possible to change the selected components and regenerate the framework.
Debugger
The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing the designer to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read and program and read and write data memory, read and write IO registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started.
Hardware Tools
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of the USB port. The base unit is universal and will operate with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation.
Design Browser
The Design Browser allows users to select and import preconfigured designs into the user's project. Users can easily browse a catalog of preconfigured designs to facilitate time-to-design. Examples provided in the tools include a 300-baud modem, LIN Bus master and slave, fan controller, and magnetic card reader.
Application Editor
In the Application Editor you can edit your C language and Assembly language source code. You can also assemble, compile, link, and build. Assembler. The macro assembler allows the assembly code to be merged seamlessly with C code. The link libraries automatically use absolute addressing or can be compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compiler. A C language compiler is available that supports Cypress MicroSystems' PSoC family devices. Even if you have never worked in the C language before, the product quickly allows you to create complete C programs for the PSoC family devices. The embedded, optimizing C compiler provides all the features of C tailored to the PSoC architecture. It comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality.
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CY8C29x66 Automotive Data Sheet
PSoC(R) Overview
Designing with User Modules
The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. Each block has several registers that determine its function and connectivity to other blocks, multiplexers, buses, and to the IO pins. Iterative development cycles permit you to adapt the hardware as well as the software. This substantially lowers the risk of having to select a different part to meet the final design requirements. To speed the development process, the PSoC Designer Integrated Development Environment (IDE) provides a library of pre-built, pre-tested hardware peripheral functions, called "User Modules." User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. The standard User Module library contains over 50 common peripherals such as ADCs, DACs Timers, Counters, UARTs, and other not-so common peripherals such as DTMF Generators and Bi-Quad analog filter sections. Each user module establishes the basic register settings that implement the selected function. It also provides parameters that allow you to tailor its precise configuration to your particular application. For example, a Pulse Width Modulator User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. User modules also provide tested software to cut your development time. The user module application programming interface (API) provides highlevel functions to control and respond to hardware events at run-time. The API also provides optional interrupt service routines that you can adapt as needed. The API functions are documented in user module data sheets that are viewed directly in the PSoC Designer IDE. These data sheets explain the internal operation of the user module and provide performance specifications. Each data sheet describes the use of each user module parameter and documents the setting of each register controlled by the user module. The development process starts when you open a new project and bring up the Device Editor, a graphical user interface (GUI) for configuring the hardware. You pick the user modules you need for your project and map them onto the PSoC blocks with point-and-click simplicity. Next, you build signal chains by interconnecting user modules to each other and the IO pins. At this stage, you also configure the clock source connections and enter parameter values directly or by selecting values from drop-down menus. When you are ready to test the hardware configuration or move on to developing code for the project, you perform the "Generate Application" step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the high-level user module API functions.
D evice E ditor
U ser M odule Selection Placem ent and Param eter -ization Source C ode G enerator
G enerate A pplication
A pplication E ditor
Project M anager Source C ode Editor Build M anager
B uild A ll
D ebugger
Interface to IC E Storage Inspector Event & Breakpoint M anager
User Module and Source Code Development Flows The next step is to write your main program, and any sub-routines using PSoC Designer's Application Editor subsystem. The Application Editor includes a Project Manager that allows you to open the project source code files (including all generated code files) from a hierarchal view. The source code editor provides syntax coloring and advanced edit features for both C and assembly language. File search capabilities include simple string searches and recursive "grep-style" patterns. A single mouse click invokes the Build Manager. It employs a professional-strength "makefile" system to automatically analyze all file dependencies and run the compiler and assembler as necessary. Project-level options control optimization strategies used by the compiler and linker. Syntax errors are displayed in a console window. Double clicking the error message takes you directly to the offending line of source code. When all is correct, the linker builds a HEX file image suitable for programming. The last step in the development process takes place inside the PSoC Designer's Debugger subsystem. The Debugger downloads the HEX file to the In-Circuit Emulator (ICE) where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, runto-breakpoint and watch-variable features, the Debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals.
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CY8C29x66 Automotive Data Sheet
PSoC(R) Overview
Document Conventions
Acronyms Used
The following table lists the acronyms that are used in this document.
Acronym AC ADC API CPU CT DAC DC ECO EEPROM FSR GPIO GUI HBM ICE ILO IMO IO IPOR LSb LVD MSb PC PLL POR PPOR PSoC(R) PWM SC SRAM alternating current analog-to-digital converter application programming interface central processing unit continuous time digital-to-analog converter direct current external crystal oscillator electrically erasable programmable read-only memory full scale range general purpose IO graphical user interface human body model in-circuit emulator internal low speed oscillator internal main oscillator input/output imprecise power on reset least-significant bit low voltage detect most-significant bit program counter phase-locked loop power on reset precision power on reset Programmable System-on-ChipTM pulse width modulator switched capacitor static random access memory Description
Table of Contents
For an in depth discussion and more information on your PSoC device, obtain the PSoC Mixed-Signal Array Technical Reference Manual. This document encompasses and is organized into the following chapters and sections. 1. Pin Information ............................................................. 8 1.1 Pinouts ................................................................... 8 1.1.1 28-Pin Part Pinout ..................................... 8 1.1.2 48-Pin Part Pinouts .................................... 9 Register Reference ..................................................... 10 2.1 Register Conventions ........................................... 10 2.1.1 Abbreviations Used .................................. 10 2.2 Register Mapping Tables ..................................... 10 Electrical Specifications ............................................ 13 3.1 Absolute Maximum Ratings ................................ 14 3.2 Operating Temperature ....................................... 14 3.3 DC Electrical Characteristics ................................ 15 3.3.1 DC Chip-Level Specifications ................... 15 3.3.2 DC General Purpose IO Specifications .... 15 3.3.3 DC Operational Amplifier Specifications ... 16 3.3.4 DC Low Power Comparator Specifications 16 3.3.5 DC Analog Output Buffer Specifications ... 17 3.3.6 DC Analog Reference Specifications ....... 18 3.3.7 DC Analog PSoC Block Specifications ..... 19 3.3.8 DC POR, and LVD Specifications ............ 19 3.3.9 DC Programming Specifications ............... 20 3.4 AC Electrical Characteristics ................................ 21 3.4.1 AC Chip-Level Specifications ................... 21 3.4.2 AC General Purpose IO Specifications .... 23 3.4.3 AC Operational Amplifier Specifications ... 24 3.4.4 AC Low Power Comparator Specifications 26 3.4.5 AC Digital Block Specifications ................. 26 3.4.6 AC Analog Output Buffer Specifications ... 27 3.4.7 AC External Clock Specifications ............. 27 3.4.8 AC Programming Specifications ............... 27 3.4.9 AC I2C Specifications ............................... 28 Packaging Information ............................................... 29 4.1 Packaging Dimensions ......................................... 29 4.2 Thermal Impedances .......................................... 30 4.3 Capacitance on Crystal Pins ............................... 30 4.4 Solder Reflow Peak Temperature ........................ 31 Ordering Information .................................................. 32 5.1 Ordering Code Definitions ................................... 32 Sales and Service Information .................................. 33 6.1 Revision History .................................................. 33 6.2 Copyrights and Flash Code Protection ................ 33
2.
3.
4.
Units of Measure
A units of measure table is located in the Electrical Specifications section. Table 3-1 on page 13 lists all the abbreviations used to measure the PSoC devices. 5. 6.
Numeric Naming
Hexidecimal numbers are represented with all letters in uppercase with an appended lowercase `h' (for example, `14h' or `3Ah'). Hexidecimal numbers may also be represented by a `0x' prefix, the C coding convention. Binary numbers have an appended lowercase `b' (e.g., 01010100b' or `01000011b'). Numbers not indicated by an `h', `b', or 0x are decimal.
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1. Pin Information
This chapter describes, lists, and illustrates the CY8C29x66 automotive PSoC device pins and pinout configurations.
1.1
Pinouts
The CY8C29x66 automotive PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a "P") is capable of Digital IO. However, Vss, Vdd, and XRES are not capable of Digital IO.
1.1.1
Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
28-Pin Part Pinout
Type
Table 1-1: 28-Pin Part Pinout (SSOP)
Digital Analog IO I IO IO IO IO IO I IO IO IO I IO I Power IO IO IO IO Power IO IO IO IO Input IO IO IO IO IO IO IO IO Power I I
Pin Name
P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] Vss P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] XRES P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd
Description
Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input.
CY8C29466 28-Pin PSoC Device
A, I, P0[7] A, IO, P0[5] A, IO, P0[3] A, I, P0[1] P2[7] P2[5] A, I, P2[3] A, I, P2[1] Vss I2CSCL, P1[7] I2C SDA, P1[5] P1[3] I2C SCL, XTALin, P1[1] Vss
Direct switched capacitor block input. Direct switched capacitor block input. Ground connection. I2C Serial Clock (SCL). I2C Serial Data (SDA). Crystal (XTALin), I2C Serial Clock (SCL), ISSP-SCLK*. Ground connection. Crystal (XTALout), I2C Serial Data (SDA), ISSP-SDATA*. Optional External Clock Input (EXTCLK). Active high external reset with internal pull down. Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND). External Voltage Reference (VREF). Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. Supply voltage.
1 2 3 4 5 6 7 8 9 10 11 12 13 14
SSOP
28 27 26 25 24 23 22 21 20 19 18 17 16 15
Vdd P0[6], A, I P0[4], A, IO P0[2], A, IO P0[0], A, I P2[6], External VREF P2[4], External AGND P2[2], A, I P2[0], A, I XRES P1[6] P1[4], EXTCLK P1[2] P1[0], XTALout, I2C SDA
I IO IO I
LEGEND: A = Analog, I = Input, and O = Output. * These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.
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CY8C29x66 Automotive Data Sheet
1. Pin Information
1.1.2
Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
48-Pin Part Pinouts
Type
Table 1-2: 48-Pin Part Pinout (SSOP)
Digital Analog IO I IO IO IO IO IO I IO IO IO I IO I IO IO IO IO Power IO IO IO IO IO IO IO IO IO IO Power IO IO IO IO IO IO IO IO IO IO Input IO IO IO IO IO IO IO IO IO IO IO IO Power
Pin Name
P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] Vss P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P3[0] P3[2] P3[4] P3[6] XRES P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd
Description
Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input.
CY8C29666 48-Pin PSoC Device
A, I, P0[7] A, IO, P0[5] A, IO, P0[3] A, I, P0[1] P2[7] P2[5] A, I, P2[3] A, I, P2[1] P4[7] P4[5] P4[3] P4[1] Vss P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] I2C SCL, P1[7] I2C SDA, P1[5] P1[3] I2C SCL, XTALin, P1[1] Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Direct switched capacitor block input. Direct switched capacitor block input.
SSOP
Ground connection.
I2C Serial Clock (SCL). I2C Serial Data (SDA). Crystal (XTALin), I2C Serial Clock (SCL), ISSP-SCLK*. Ground connection. Crystal (XTALout), I2C Serial Data (SDA), ISSP-SDATA*. Optional External Clock Input (EXTCLK).
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
Vdd P0[6], A, I P0[4], A, IO P0[2], A, IO P0[0], A, I P2[6], External VREF P2[4], External AGND P2[2], A, I P2[0], A, I P4[6] P4[4] P4[2] P4[0] XRES P3[6] P3[4] P3[2] P3[0] P5[2] P5[0] P1[6] P1[4], EXTCLK P1[2] P1[0], XTALout, I2C SDA
Active high external reset with internal pull down.
I I
I IO IO I
Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND). External Voltage Reference (VREF). Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. Supply voltage.
LEGEND: A = Analog, I = Input, and O = Output. * These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.
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2. Register Reference
This chapter lists the registers of the CY8C29x66 automotive PSoC device. For detailed register information, reference the PSoC Mixed-Signal Array Technical Reference Manual.
2.1
2.1.1
Register Conventions
Abbreviations Used
2.2
Register Mapping Tables
The register conventions specific to this section are listed in the following table.
Convention R W L C # Description Read register or bit(s) Write register or bit(s) Logical register or bit(s) Clearable register or bit(s) Access is bit specific
The PSoC device has a total register address space of 512 bytes. The register space is referred to as IO space and is divided into two banks. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user is in Bank 1. Note In the following register mapping tables, blank fields are Reserved and should not be accessed.
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2. Register Reference
Register Map Bank 0 Table: User Space
Access Access Access Access Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Name Name Name Name
00 RW DBB20DR0 40 01 RW DBB20DR1 41 02 RW DBB20DR2 42 03 RW DBB20CR0 43 04 RW DBB21DR0 44 05 RW DBB21DR1 45 06 RW DBB21DR2 46 07 RW DBB21CR0 47 08 RW DCB22DR0 48 09 RW DCB22DR1 49 0A RW DCB22DR2 4A 0B RW DCB22CR0 4B 0C RW DCB23DR0 4C 0D RW DCB23DR1 4D 0E RW DCB23DR2 4E 0F RW DCB23CR0 4F 10 RW DBB30DR0 50 11 RW DBB30DR1 51 12 RW DBB30DR2 52 13 RW DBB30CR0 53 14 RW DBB31DR0 54 15 RW DBB31DR1 55 16 RW DBB31DR2 56 17 RW DBB31CR0 57 18 DCB32DR0 58 19 DCB32DR1 59 1A DCB32DR2 5A 1B DCB32CR0 5B 1C DCB33DR0 5C 1D DCB33DR1 5D 1E DCB33DR2 5E 1F DCB33CR0 5F DBB00DR0 20 # AMX_IN 60 DBB00DR1 21 W 61 DBB00DR2 22 RW 62 DBB00CR0 23 # ARF_CR 63 DBB01DR0 24 # CMP_CR0 64 DBB01DR1 25 W ASY_CR 65 DBB01DR2 26 RW CMP_CR1 66 DBB01CR0 27 # 67 DCB02DR0 28 # 68 DCB02DR1 29 W 69 DCB02DR2 2A RW 6A DCB02CR0 2B # 6B DCB03DR0 2C # TMP_DR0 6C DCB03DR1 2D W TMP_DR1 6D DCB03DR2 2E RW TMP_DR2 6E DCB03CR0 2F # TMP_DR3 6F DBB10DR0 30 # ACB00CR3 70 DBB10DR1 31 W ACB00CR0 71 DBB10DR2 32 RW ACB00CR1 72 DBB10CR0 33 # ACB00CR2 73 DBB11DR0 34 # ACB01CR3 74 DBB11DR1 35 W ACB01CR0 75 DBB11DR2 36 RW ACB01CR1 76 DBB11CR0 37 # ACB01CR2 77 DCB12DR0 38 # ACB02CR3 78 DCB12DR1 39 W ACB02CR0 79 DCB12DR2 3A RW ACB02CR1 7A DCB12CR0 3B # ACB02CR2 7B DCB13DR0 3C # ACB03CR3 7C DCB13DR1 3D W ACB03CR0 7D DCB13DR2 3E RW ACB03CR1 7E DCB13CR0 3F # ACB03CR2 7F Blank fields are Reserved and should not be accessed.
PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2
# W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # RW
RW # # RW
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 MUL1_X A8 MUL1_Y A9 MUL1_DH AA MUL1_DL AB ACC1_DR1 AC ACC1_DR0 AD ACC1_DR3 AE ACC1_DR2 AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDI0LT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 RDI1RI B8 RDI1SYN B9 RDI1IS BA RDI1LT0 BB RDI1LT1 BC RDI1RO0 BD RDI1RO1 BE BF # Access is bit specific.
ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI3RI RDI3SYN RDI3IS RDI3LT0 RDI3LT1 RDI3RO0 RDI3RO1 CUR_PP STK_PP IDX_PP MVR_PP MVW_PP I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH DEC_DL DEC_CR0 DEC_CR1 MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2
W W R R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
CPU_F
CPU_SCR1 CPU_SCR0
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW # RW # RW RW RW RW RW RW RW RW RC W RC RC RW RW W W R R RW RW RW RW
RL
# #
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2. Register Reference
Register Map Bank 1 Table: Configuration Space
Access Access Access Access Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Name Name Name Name
00 RW DBB20FN 40 01 RW DBB20IN 41 02 RW DBB20OU 42 03 RW 43 04 RW DBB21FN 44 05 RW DBB21IN 45 06 RW DBB21OU 46 07 RW 47 08 RW DCB22FN 48 09 RW DCB22IN 49 0A RW DCB22OU 4A 0B RW 4B 0C RW DCB23FN 4C 0D RW DCB23IN 4D 0E RW DCB23OU 4E 0F RW 4F 10 RW DBB30FN 50 11 RW DBB30IN 51 12 RW DBB30OU 52 13 RW 53 14 RW DBB31FN 54 15 RW DBB31IN 55 16 RW DBB31OU 56 17 RW 57 18 DCB32FN 58 19 DCB32IN 59 1A DCB32OU 5A 1B 5B 1C DCB33FN 5C 1D DCB33IN 5D 1E DCB33OU 5E 1F 5F DBB00FN 20 RW CLK_CR0 60 DBB00IN 21 RW CLK_CR1 61 DBB00OU 22 RW ABF_CR0 62 23 AMD_CR0 63 DBB01FN 24 RW 64 DBB01IN 25 RW 65 DBB01OU 26 RW AMD_CR1 66 27 ALT_CR0 67 DCB02FN 28 RW ALT_CR1 68 DCB02IN 29 RW CLK_CR2 69 DCB02OU 2A RW 6A 2B 6B DCB03FN 2C RW TMP_DR0 6C DCB03IN 2D RW TMP_DR1 6D DCB03OU 2E RW TMP_DR2 6E 2F TMP_DR3 6F DBB10FN 30 RW ACB00CR3 70 DBB10IN 31 RW ACB00CR0 71 DBB10OU 32 RW ACB00CR1 72 33 ACB00CR2 73 DBB11FN 34 RW ACB01CR3 74 DBB11IN 35 RW ACB01CR0 75 DBB11OU 36 RW ACB01CR1 76 37 ACB01CR2 77 DCB12FN 38 RW ACB02CR3 78 DCB12IN 39 RW ACB02CR0 79 DCB12OU 3A RW ACB02CR1 7A 3B ACB02CR2 7B DCB13FN 3C RW ACB03CR3 7C DCB13IN 3D RW ACB03CR0 7D DCB13OU 3E RW ACB03CR1 7E 3F ACB03CR2 7F Blank fields are Reserved and should not be accessed.
PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
RW RW RW RW
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDI0LT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 RDI1RI B8 RDI1SYN B9 RDI1IS BA RDI1LT0 BB RDI1LT1 BC RDI1RO0 BD RDI1RO1 BE BF # Access is bit specific.
ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
RW RW RW RW RW RW RW RW RW RW RW RW RW RW
C0 C1 C2 C3 C4 C5 C6 C7 RDI3RI C8 RDI3SYN C9 RDI3IS CA RDI3LT0 CB RDI3LT1 CC RDI3RO0 CD RDI3RO1 CE CF GDI_O_IN D0 GDI_E_IN D1 GDI_O_OU D2 GDI_E_OU D3 D4 D5 D6 D7 D8 D9 DA DB DC OSC_GO_EN DD OSC_CR4 DE OSC_CR3 DF OSC_CR0 E0 OSC_CR1 E1 OSC_CR2 E2 VLT_CR E3 VLT_CMP E4 E5 E6 E7 IMO_TR E8 ILO_TR E9 BDG_TR EA ECO_TR EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 CPU_F F7 F8 F9 FLS_PR1 FA FB FC FD CPU_SCR1 FE CPU_SCR0 FF
RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
RW RW RW RW RW RW RW R
W W RW W
RL
RW
# #
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3. Electrical Specifications
This chapter presents the DC and AC electrical specifications of the CY8C29x66 automotive PSoC device. For the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc. Specifications are valid for -40oC TA 125oC and TJ 135oC, except where noted.
5.25
4.75 Vdd Voltage 3.00 93 kHz
Valid Operating Region
12 MHz CPU Frequency
24 MHz
Figure 3-1. Voltage versus CPU Frequency
The following table lists the units of measure that are used in this chapter. Table 3-1: Units of Measure
Symbol
o
Unit of Measure degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square
Symbol
W
Unit of Measure microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts ohm picoampere picofarad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volts
C
dB fF Hz KB Kbit kHz k MHz M
A F H s V Vrms
mA ms mV nA ns nV
pA pF pp ppm ps sps
V
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3. Electrical Specifications
3.1
Symbol TSTG
Absolute Maximum Ratings
Description Storage Temperature Min -55 Typ +25 Max +125 Units
C
Table 3-2: Absolute Maximum Ratings
Notes Higher storage temperatures will reduce data retention time. Recommended storage temperature is +25C 25C. Storage temperatures above 65oC will degrade reliability. Maximum combined storage and operational time at +125C is 7000 hours.
TA Vdd VIO VIOZ IMIO ESD LU
Ambient Temperature with Power Applied Supply Voltage on Vdd Relative to Vss DC Input Voltage DC Voltage Applied to Tri-state Maximum Current into any Port Pin Electro Static Discharge Voltage Latch-up Current
-40 -0.5 Vss - 0.5 Vss - 0.5 -25 2000 -
- - - - - - -
+125 +5.75
o
C
V
Vdd + 0.5 V Vdd + 0.5 V +25 - 200 mA V mA Human Body Model ESD.
3.2
Symbol TA TJ
Operating Temperature
Description Ambient Temperature Junction Temperature Min -40 -40 - - Typ Max +125 +135
o o
Table 3-3: Operating Temperature
Units C C The temperature rise from ambient to junction is package specific. See "Thermal Impedances" on page 30. The user must limit the power consumption to comply with this requirement. Notes
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3. Electrical Specifications
3.3
3.3.1
DC Electrical Characteristics
DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 125C. Typical parameters apply to 5V at 25C and are for design guidance only. Table 3-4: DC Chip-Level Specifications
Symbol Vdd IDD Supply Voltage Supply Current Description - Min 4.75 - 8 Typ 15 Max 5.25 V mA Conditions are Vdd=5.25V, -40 oC TA 125oC, CPU=3 MHz, SYSCLK doubler disabled. VC1=1.5 MHz, VC2=93.75 kHz, VC3=0.366 kHz. Analog power = off. Conditions are with internal slow speed oscillator, Vdd = 5.25V, -40 oC TA 55 oC. Analog power = off. Conditions are with internal slow speed oscillator, Vdd = 5.25V, 55 oC < TA 125 oC. Analog power = off. Conditions are with properly loaded, 1 W max, 32.768 kHz crystal. Vdd = 5.25V, -40 oC TA 55oC. Analog power = off. - 8 100
A
Units
Notes
ISB
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and internal slow oscillator active. Lower 3/4 temperature range. Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and internal slow oscillator active. Higher 1/4 temperature range (hot). Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, internal slow oscillator, and 32 kHz crystal oscillator active. Lower 3/4 temperature range. Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and 32 kHz crystal oscillator active. Higher 1/4 temperature range (hot). Reference Voltage (Bandgap)
-
6
16
A
ISBH
-
6
100
A
ISBXTL
-
8
18
A
ISBXTLH
Conditions are with properly loaded, 1 W max, 32.768 kHz crystal. Vdd = 5.25V, 55 oC < TA 125oC. Analog power = off.
VREF
1.25
1.3
1.35
V
3.3.2
DC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 125C. Typical parameters apply to 5V at 25C and are for design guidance only. Table 3-5: DC GPIO Specifications
Symbol RPU RPD VOH Pull-up Resistor Pull-down Resistor High Output Level Description 4 4 3.5 Min Typ 5.6 5.6 - 8 8 - Max Units k k V IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). Vdd = 4.75 to 5.25. Vdd = 4.75 to 5.25. Gross tested to 1 A. Package and pin dependent. Temp = 25oC. Package and pin dependent. Temp = 25oC. Notes
VOL
Low Output Level
-
-
0.75
V
VIL VIH VH IIL CIN COUT
Input Low Level Input High Level Input Hysterisis Input Leakage (Absolute Value) Capacitive Load on Pins as Input Capacitive Load on Pins as Output
- 2.2 - - - -
- - 110 1 3.5 3.5
0.8 - - 10 10
V V mV nA pF pF
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3. Electrical Specifications
3.3.3
DC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 125C. Typical parameters apply to 5V at 25C and are for design guidance only. The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Table 3-6: DC Operational Amplifier Specifications
Symbol VOSOA Description Input Offset Voltage (absolute value) Low Power Input Offset Voltage (absolute value) Mid Power Input Offset Voltage (absolute value) High Power TCVOSOA IEBOA CINOA VCMOA Input Offset Voltage Drift Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) Common Mode Voltage Range. All Cases, except highest. Power = High, Opamp Bias = High GOLOA VOHIGHOA VOLOWOA ISOA Open Loop Gain High Output Voltage Swing (worst case internal load) Low Output Voltage Swing (worst case internal load) Supply Current (including associated AGND buffer) Power=Low Power=Low, Opamp Bias=High Power=Medium Power=Medium, Opamp Bias=High Power=High Power=High, Opamp Bias=High PSRROA Supply Voltage Rejection Ratio - - - - - - - 150 300 600 1210 2400 4600 80 200 800 800 1700 3200 6800 -
A A A A A A
Min - - - - - - 0.0 0.5 - Vdd - 0.2 -
Typ 1.6 1.3 1.2 7.0 200 4.5 - - 80 - - 19 11 11
Max
Units mV mV mV
V/oC
Notes Opamp Bias = High.
35.0 - 10 Vdd Vdd - 0.5 - - 0.2
pA pF V V dB V V
Gross tested to 1 A. Package and pin dependent. Temp = 25oC.
dB
Vss VIN (Vdd - 2.25) or (Vdd - 1.25V) VIN Vdd.
3.3.4
DC Low Power Comparator Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 125C. Typical parameters apply to 5V at 25C and are for design guidance only. Table 3-7. DC Low Power Comparator Specifications
Symbol VREFLPC ISLPC VOSLPC LPC supply current LPC voltage offset Description Low power comparator (LPC) reference voltage range - - Min 0.2 - 10 2.5 Typ 40 30 Max Vdd - 1 V
A
Units
Notes
mV
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3. Electrical Specifications
3.3.5
DC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 125C. Typical parameters apply to 5V at 25C and are for design guidance only. Table 3-8: DC Analog Output Buffer Specifications
Symbol VOSOB TCVOSOB VCMOB ROUTOB VOHIGHOB VOLOWOB ISOB Description Input Offset Voltage (Absolute Value) Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance High Output Voltage Swing (Load = 32 ohms to Vdd/2) Low Output Voltage Swing (Load = 32 ohms to Vdd/2) Supply Current Including Bias Cell (No Load) Power = Low Power = High PSRROB Supply Voltage Rejection Ratio - - - 1.1 2.6 64 5.1 8.8 - mA mA dB - - 0.5 - Min 3 +6 - 1 Typ 19 - Vdd - 1.0 - - 0.5 x Vdd - 1.3 Max Units mV
V/C
Notes
V
0.5 x Vdd + 1.3 - - -
V V
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3. Electrical Specifications
3.3.6
DC Analog Reference Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 125C. Typical parameters apply to 5V at 25C and are for design guidance only. The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block. Table 3-9: DC Analog Reference Specifications
Symbol VBG5 - - - - - - - - - - - - - - - - - - AGND = Vdd/2a CT Block Power = High AGND = 2 x BandGapa CT Block Power = High AGND = P2[4] (P2[4] = Vdd/2)a CT Block Power = High AGND = BandGapa CT Block Power = High AGND = 1.6 x BandGapa CT Block Power = High AGND Column to Column Variation (AGND=Vdd/2)a CT Block Power = High RefHi = Vdd/2 + BandGap Ref Control Power = High RefHi = 3 x BandGap Ref Control Power = High RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) Ref Control Power = High RefHi = P2[4] + BandGap (P2[4] = Vdd/2) Ref Control Power = High RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) Ref Control Power = High RefHi = 2 x BandGap Ref Control Power = High RefHi = 3.2 x BandGap Ref Control Power = High RefLo = Vdd/2 - BandGap Ref Control Power = High RefLo = BandGap Ref Control Power = High RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) Ref Control Power = High RefLo = P2[4] - BandGap (P2[4] = Vdd/2) Ref Control Power = High RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) Ref Control Power = High P2[4] - P2[6] - 0.1 P2[4] - P26 P2[4] - P2[6] + 0.1 V P2[4] - 1.45 P2[4] - 1.3 P2[4] - 1.15 V 2.4 - P2[6] 2.6 - P2[6] 2.8 + P2[6] V 1.15 1.30 1.45 V 3.9 4.16 4.42 V V 2.4 2.60 2.8 V P2[4] + P2[6] - 0.1 P2[4] + P2[6] P2[4] + P2[6] + 0.1 V P2[4] + 1.24 P2[4] + 1.30 P2[4] + 1.36 V P2[6] + 2.4 P2[6] + 2.6 P2[6] + 2.8 V 3.65 3.9 4.15 V - 0.035 0.000 0.035 V V 1.98 2.08 2.14 V 1.23 1.3 1.37 V P2[4] - 0.02 P2[4] P2[4] + 0.02 V 2.4 2.60 2.8 V Vdd/2 - 0.02 Vdd/2 Vdd/2 + 0.02 V Description Bandgap Voltage Reference 5V 1.25 Min 1.30 Typ 1.35 Max V Units
Vdd/2 + 1.15
Vdd/2 + 1.30
Vdd/2 + 1.45
Vdd/2 - 1.45
Vdd/2 - 1.3
Vdd/2 - 1.15
a. AGND tolerance includes the offsets of the local buffer in the PSoC block. BG = Bandgap voltage is 1.3V 0.05V.
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3. Electrical Specifications
3.3.7
DC Analog PSoC Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 125C. Typical parameters apply to 5V at 25C and are for design guidance only. Table 3-10: DC Analog PSoC Block Specifications
Symbol RCT CSC Description Resistor Unit Value (Continuous Time) Capacitor Unit Value (Switch Cap) - - Min 80 Typ 12.24 - - Max fF Units k Notes
3.3.8
DC POR, and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 125C. Typical parameters apply to 5V at 25C and are for design guidance only. Table 3-11: DC POR, and LVD Specifications
Symbol VPPOR1R VPPOR2R VPPOR1 VPPOR2 VPH1 VPH2 VLVD6 VLVD7 PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for PPOR Trip (negative ramp) PORLEV[1:0] = 01b PORLEV[1:0] = 10b PPOR Hysteresis PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for LVD Trip VM[2:0] = 110b VM[2:0] = 111b 4.65 4.75 4.80 4.90 4.90 5.00 V V - - 0 0 - - mV mV - 4.40 4.60 - V V Description Vdd Value for PPOR Trip (positive ramp) - 4.40 4.60 - V V Min Typ Max Units Notes
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3. Electrical Specifications
3.3.9
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 125C. Typical parameters apply to 5V at 25C and are for design guidance only. Table 3-12: DC Programming Specifications
Symbol IDDP VILP VIHP IILP IIHP VOLV VOHV FlashENPB FlashENT FlashDR Description Supply Current During Programming or Verify Input Low Voltage During Programming or Verify Input High Voltage During Programming or Verify Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify Input Current when Applying Vihp to P1[0] or P1[1] During Programming or Verify Output Low Voltage During Programming or Verify Output High Voltage During Programming or Verify Flash Endurance (per
c
Min - - 2.2 - - - 3.5 100 51,200 15 15 - - - - - - - - -
Typ 30 0.8 - 0.2 1.5
Max V V
Units mA
Notes
mA mA
Driving internal pull-down resistor. Driving internal pull-down resistor.
Vss + 0.75 V Vdd - - - V - - Years Erase/write cycles per block. Erase/write cycles.
block)a
a,b
Flash Endurance (total) Flash Data Retention
a. For the full temperature range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information. b. A maximum of 512 x 100 block endurance cycles is allowed. c. Flash data retention based on the use condition of 7000 hours at TA 125C and the remaining time at TA 65C.
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3. Electrical Specifications
3.4
3.4.1
AC Electrical Characteristics
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 125C. Typical parameters apply to 5V at 25C and are for design guidance only. Table 3-13: AC Chip-Level Specifications
Symbol FIMO24 FCPU1 F48M F24M F32K1 F32K2 FPLL Jitter24M2 TPLLSLEW TPLLSLEWSLOW
Description Internal Main Oscillator Frequency for 24 MHz CPU Frequency (5V Nominal) Digital PSoC Block Frequency Digital PSoC Block Frequency Internal Low Speed Oscillator Frequency External Crystal Oscillator PLL Frequency 24 MHz Period Jitter (PLL) PLL Lock Time PLL Lock Time for Low Gain Setting External Crystal Oscillator Startup to 1% External Crystal Oscillator Startup to 200 ppm 32 kHz Period Jitter External Reset Pulse Width 24 MHz Duty Cycle 24 MHz Trim Step Size 24 MHz Period Jitter (IMO) Peak-to-Peak 24 MHz Period Jitter (IMO) Root Mean Squared Maximum frequency of signal on row input or row output. Supply Ramp Time
Min 22.95 0.09 - 0 15 - - - 0.5 0.5 - - - 10 40 - - - - 0 24 12 - 24 32
Typ
Max 24.96
12.48
Units MHz MHz MHz MHz kHz kHz MHz ps ms ms ms ms ns
s
Notes Trimmed. Utilizing factory trim values. Not allowed.
-
24.96a
64 - - 800 10 50 2620 3800 - 60 - 600 12.48 -
32.768 23.986 - - - 1700 2800 100 - 50 50 300 - - -
Accuracy is capacitor and crystal dependent. Is a multiple (x732) of crystal frequency.
TOS TOSACC Jitter32k TXRST DC24M Step24M Jitter24M1P Jitter24M1R FMAX TRAMP
% kHz ps ps MHz
s
a. See the individual user module data sheets for information on maximum frequencies for user modules.
PLL Enable
TPLLSLEW 24 MHz
FPLL PLL Gain
0
Figure 3-2. PLL Lock Timing Diagram
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3. Electrical Specifications
PLL Enable
TPLLSLEWLOW 24 MHz
FPLL PLL Gain
1
Figure 3-3. PLL Lock for Low Gain Setting Timing Diagram
32K Select
TOS
32 kHz
F32K2
Figure 3-4. External Crystal Oscillator Startup Timing Diagram
Jitter24M1
F24M
Figure 3-5. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter32k
F32K2
Figure 3-6. 32 kHz Period Jitter (ECO) Timing Diagram
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3. Electrical Specifications
3.4.2
AC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 125C. Typical parameters apply to 5V at 25C and are for design guidance only.
Table 3-14: AC GPIO Specifications
Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload = 50 pF Fall Time, Normal Strong Mode, Cload = 50 pF Rise Time, Slow Strong Mode, Cload = 50 pF Fall Time, Slow Strong Mode, Cload = 50 pF 0 3 2 9 9 Min - - - 27 22 Typ 22 22 - - Max 12.48 Units MHz ns ns ns ns Notes Normal Strong Mode Vdd = 4.75 to 5.25V, 10% - 90% Vdd = 4.75 to 5.25V, 10% - 90% Vdd = 4.75 to 5.25V, 10% - 90% Vdd = 4.75 to 5.25V, 10% - 90%
90% GPIO Pin Output Voltage 10%
TRiseF TRiseS
TFallF TFallS
Figure 3-7. GPIO Timing Diagram
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3. Electrical Specifications
3.4.3
AC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 125C. Typical parameters apply to 5V at 25C and are for design guidance only. Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Table 3-15: AC Operational Amplifier Specifications
Symbol SRROA Description Rising Slew Rate (20% to 80%) of a 1V Step (10 pF load, Unity Gain) Power = Low Power = Low, Opamp Bias = High Power = Medium Power = Medium, Opamp Bias = High Power = High Power = High, Opamp Bias = High SRFOA Falling Slew Rate (20% to 80%) of a 1V Step (10 pF load, Unity Gain) Power = Low Power = Low, Opamp Bias = High Power = Medium Power = Medium, Opamp Bias = High Power = High Power = High, Opamp Bias = High BWOA Gain Bandwidth Product Power = Low Power = Low, Opamp Bias = High Power = Medium Power = Medium, Opamp Bias = High Power = High Power = High, Opamp Bias = High 0.75 0.75 0.75 3.1 3.1 5.4 - - - MHz MHz MHz MHz MHz MHz 0.01 0.01 0.01 0.5 0.5 4.0 - - - V/s V/s V/s V/s V/s V/s 0.15 0.15 0.15 1.7 1.7 6.5 - - - V/s V/s V/s V/s V/s V/s Min Typ Max Units Notes
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3. Electrical Specifications
When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.
dBV/rtHz 10000
0 0.01 0.1 1.0 10
1000
100 0.001
0.01
0.1 Freq (kHz)
1
10
100
Figure 3-8. Typical AGND Noise with P2[4] Bypass
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high frequencies, increased power level reduces the noise spectrum level.
nV/rtHz 10000 PH_BH PH_BL PM_BL PL_BL 1000
100
10 0.001
0.01
0.1
Freq (kHz)
1
10
100
Figure 3-9. Typical Opamp Noise
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3. Electrical Specifications
3.4.4
AC Low Power Comparator Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 125C. Typical parameters apply to 5V at 25C and are for design guidance only.
Table 3-16. AC Low Power Comparator Specifications
Symbol TRLPC LPC response time Description - Min - Typ 50 Max Units
s
Notes
50 mV overdrive comparator reference set within VREFLPC.
3.4.5
AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 125C. Typical parameters apply to 5V at 25C and are for design guidance only.
Table 3-17: AC Digital Block Specifications
Function All Functions Timer Description Maximum Block Clocking Frequency (> 4.75V) Capture Pulse Width Maximum Frequency, No Capture Maximum Frequency, With Capture Counter Enable Pulse Width Maximum Frequency, No Enable Input Maximum Frequency, Enable Input Dead Band Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency CRCPRS Maximum Input Clock Frequency (PRS Mode) CRCPRS Maximum Input Clock Frequency (CRC Mode) SPIM SPIS Maximum Input Clock Frequency Maximum Input Clock Frequency Width of SS_ Negated Between Transmissions Transmitter Receiver Maximum Input Clock Frequency Maximum Input Clock Frequency 20 50a 50a - - - - - 50 - -
a
Min
Typ
Max 24.96
Units MHz ns MHz MHz ns MHz MHz ns ns ns MHz MHz MHz MHz MHz ns MHz MHz
Notes 4.75V < Vdd < 5.25V.
50a - - 50a - -
- - - - - - - - - - - - - - - - 16
- 24.96 24.96 - 24.96 24.96 - - - 24.96 24.96 24.96 4 2 - 8 24.96
4.75V < Vdd < 5.25V.
4.75V < Vdd < 5.25V.
4.75V < Vdd < 5.25V. 4.75V < Vdd < 5.25V.
Maximum data rate at 4.1 MHz due to 2 x over clocking.
Maximum data rate at 3.08 MHz due to 8 x over
clocking. clocking.
Maximum data rate at 3.08 MHz due to 8 x over
a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
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3. Electrical Specifications
3.4.6
AC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 125C. Typical parameters apply to 5V at 25C and are for design guidance only.
Table 3-18: AC Analog Output Buffer Specifications
Symbol TROB Power = Low Power = High TSOB Falling Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High SRROB Rising Slew Rate (20% to 80%), 1V Step, 100pF Load Power = Low Power = High SRFOB Falling Slew Rate (80% to 20%), 1V Step, 100pF Load Power = Low Power = High BWOB Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load Power = Low Power = High BWOB Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load Power = Low Power = High 300 300 - - - - kHz kHz 0.8 0.8 - - - - MHz MHz 0.6 0.6 - - - - V/s V/s 0.6 0.6 - - - - V/s V/s - - - - 4 4
s s
Description Rising Settling Time to 0.1%, 1V Step, 100pF Load - -
Min - -
Typ 4 4
Max
Units
s s
Notes
3.4.7
AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 125C. Typical parameters apply to 5V at 25C and are for design guidance only.
Table 3-19: AC External Clock Specifications
Symbol FOSCEXT - - - Frequency High Period Low Period Power Up IMO to Switch Description 0 20.6 20.6 150 Min - - - - Typ - - - Max 24.24 Units MHz ns ns
s
Notes
3.4.8
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 125C. Typical parameters apply to 5V at 25C and are for design guidance only.
Table 3-20: AC Programming Specifications
Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK Rise Time of SCLK Fall Time of SCLK Data Set up Time to Falling Edge of SCLK Data Hold Time from Falling Edge of SCLK Frequency of SCLK Flash Erase Time (Block) Flash Block Write Time Data Out Delay from Falling Edge of SCLK Description 1 1 40 40 0 - - - Min - - - - - 15 30 - Typ 20 20 - - 8 - - 45 Max Units ns ns ns ns MHz ms ms ns Notes
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3. Electrical Specifications
3.4.9
AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 125C. Typical parameters apply to 5V at 25C and are for design guidance only.
Table 3-21: AC Characteristics of the I2C SDA and SCL Pins
Standard Mode Symbol FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C Description SCL Clock Frequency Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. LOW Period of the SCL Clock HIGH Period of the SCL Clock Set-up Time for a Repeated START Condition Data Hold Time Data Set-up Time Set-up Time for STOP Condition Pulse Width of spikes are suppressed by the input filter. 0 4.0 4.7 4.0 4.7 0 250 4.0 - Min - - - - - - - - - Max 100 0 0.6 1.3 0.6 0.6 0 100a 0.6 1.3 0 Fast Mode Min - - - - - - - - 50 Max 400 Units kHz
s s s s s
Notes
ns
s s
Bus Free Time Between a STOP and START Condition 4.7
ns
a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
SDA
TLOWI2C
TSUDATI2C
THDSTAI2C
TSPI2C
TBUFI2C
SCL S THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C Sr TSUSTOI2C P S
Figure 3-10. Definition for Timing for Fast/Standard Mode on the I2C Bus
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4. Packaging Information
This chapter illustrates the packaging specifications for the CY8C29x66 automotive PSoC device, along with the thermal impedances and solder reflow for each package and the typical package capacitance on crystal pins.
Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation tools' dimensions, refer to the document titled PSoC Emulator Pod Dimensions at http://www.cypress.com/design/MR10161.
4.1
Packaging Dimensions
51-85079 *C
Figure 4-1. 28-Lead (210-Mil) SSOP
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4. Packaging Information
51-85061 *C 51-85061-C
Figure 4-2. 48-Lead (300-Mil) SSOP
4.2
Thermal Impedances
Package 28 SSOP 48 SSOP Typical
o
Table 4-1: Thermal Impedances per Package JA *
95 C/W 69 oC/W
* TJ = TA + POWER x JA
4.3
Capacitance on Crystal Pins
Package 28 SSOP 48 SSOP Package Capacitance 2.8 pF 3.3 pF
Table 4-2: Typical Package Capacitance on Crystal Pins
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4. Packaging Information
4.4
Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability.
Table 4-3. Solder Reflow Peak Temperature
Package 28 SSOP 48 SSOP Minimum Peak Temperature* 240 C 220oC
o
Maximum Peak Temperature 260oC 260oC
*Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 5oC with Sn-Pb or 245 5oC with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications.
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5. Ordering Information
The following table lists the CY8C29x66 PSoC device's key package features and ordering codes.
Table 5-1: CY8C29x66 Automotive PSoC Key Features and Ordering Information
Analog PSoC Blocks Temperature Range Digital PSoC Blocks XRES Pin Yes Yes Yes Yes Digital IO Pins Ordering Code Package Analog Outputs 4 4 4 4 Flash (Bytes) RAM (Bytes) Analog Inputs 12 12 12 12
28 Pin (210 Mil) SSOP 28 Pin (210 Mil) SSOP (Tape and Reel) 48 Pin (300 Mil) SSOP 48 Pin (300 Mil) SSOP (Tape and Reel)
CY8C29466-12PVXE CY8C29466-12PVXET CY8C29666-12PVXE CY8C29666-12PVXET
32K 32K 32K 32K
2K 2K 2K 2K
-40C to +125C -40C to +125C -40C to +125C -40C to +125C
16 16 16 16
12 12 12 12
24 24 44 44
5.1
Ordering Code Definitions
Package Type: Thermal Rating: PX = PDIP Pb-Free C = Commercial SX = SOIC Pb-Free I = Industrial PVX = SSOP Pb-Free E = Extended LFX/LKX = QFN Pb-Free AX = TQFP Pb-Free Speed: 12 MHz Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = Cypress PSoC Company ID: CY = Cypress
CY 8 C 29 xxx-SPxx
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6. Sales and Service Information
To obtain information about Cypress Semiconductor or PSoC sales and technical support, reference the following information.
Cypress Semiconductor 198 Champion Court San Jose, CA 95134 408.943.2600
Web Sites:
Company Information - http://www.cypress.com Sales - http://www.cypress.com/aboutus/sales_locations.cfm Technical Support - http://www.cypress.com/support/login.cfm
6.1
Revision History
CY8C29466 and CY8C29666 Automotive PSoC(R) Mixed-Signal Array Final Data Sheet 38-12026 Issue Date 06/01/2004 See ECN See ECN See ECN Origin of Change SFV HMT HMT HMT Description of Change First release of the CY8C29x66 automotive PSoC device data sheet. Update per SFV memo. Input changes from MWR, including removing SMP. Add Reflow Peak Temp. table. Update PSoC Characteristics table. Update characterization data. Update PSoC Characteristics table. Update characterization data. Update Storage Temperature for extended temperature devices. Fix error in Register Bank 0/1. Update CY color, logo and copyright. Add Low Power Comparator (LPC) AC/DC electrical spec. tables. Add CY8C20x34 to PSoC Device Characteristics table. Update Technical Training Modules paragraph. Add ISSP note to pinout tables. ECN # 228771 271452 288029 473829
Table 6-1: CY8C29x66 Automotive Data Sheet Revision History
Document Title: Document Number: Revision ** *A *B *C
*D
602219
See ECN
HMT
Distribution: External/Public
Posting: None
6.2
Copyrights and Flash Code Protection
(c) Cypress Semiconductor Corporation. 2004-2006. All rights reserved. PSoC DesignerTM, Programmable System-on-ChipTM, and PSoC ExpressTM are trademarks and PSoC(R) is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. The information contained herein is subject to change without notice. Cypress Semiconductor assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Cypress Semiconductor products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress Semiconductor. Note the following details of the Flash code protection features on Cypress Semiconductor PSoC devices. Cypress Semiconductor products meet the specifications contained in their particular Cypress Semiconductor Data Sheets. Cypress Semiconductor believes that its family of products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress Semiconductor, that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress Semiconductor nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Cypress Semiconductor is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress Semiconductor are committed to continuously improving the code protection features of our products.
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